Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
ID.v		ID.v
README.md		README.md
decoder.v		decoder.v
decoder_tb.v		decoder_tb.v
multiplexer.v		multiplexer.v
register_file.v		register_file.v
register_file_tb.v		register_file_tb.v
sign_extend.v		sign_extend.v
sign_extender_tb.v		sign_extender_tb.v

Repository files navigation

ComputerArchitecture

Finished

Register File
Sign Extender
2x1 Multiplexer

To do

Instruction Decode
Control Signals

About

No description, website, or topics provided.

Report repository

Releases

No releases published

Packages

No packages published

Languages

Verilog 100.0%