Computer Engineering @ Toronto Metropolitan University
Specializing in building high-fidelity trading infrastructure and low-latency systems.
Infrastructure
Python Pandas Polars Event-Driven Architecture Monte Carlo Methods
Systems Engineering
C++20 Lock-free Data Structures Multithreading Ring Buffers
Hardware & FPGA
VHDL Quartus II Computer Architecture RTL Design
🔹 Meridian
Deterministic backtesting engine for intraday futures strategies.
Python, Event-Driven Architecture, Quantitative Finance
- Features: Regime-adaptive slippage, strict session handling (America/New_York), and causal integrity enforcement.
- Performance: Validated on Strategy 3A (0.20 R Expectancy / 1.69 SQN).
- Engineering: Full CI/CD pipeline, type-strict codebase, and semantic reproducibility.
A high-performance Limit Order Book (LOB) matching engine designed for microsecond-level latency simulation.
C++, Market Microstructure, HFT
In Development (Q1 2026).
- Architecture: Utilizes ring buffers and pre-allocated memory pools for zero-allocation execution.
Implementation of a custom processor architecture on FPGA.
VHDL, Quartus II, Hardware Design
- Focus: ALU design, instruction pipelining, and register transfer level (RTL) logic.