Processor

Single cycle processor design in VHDL that implements simpleRisc ISA.

SimpleRisc ISA is a reduced instruction set which is similar to ARM ISA.

to run, type $ ./run.sh <input_machine_code_file> in your command line

Name		Name	Last commit message	Last commit date
Latest commit History 19 Commits
html		html
latex		latex
testcodes		testcodes
CUnit.o		CUnit.o
CUnit.vhdl		CUnit.vhdl
Check.ghw		Check.ghw
EXUnit.o		EXUnit.o
EXUnit.vhdl		EXUnit.vhdl
IFUnit.o		IFUnit.o
IFUnit.vhdl		IFUnit.vhdl
MAUnit.o		MAUnit.o
MAUnit.vhdl		MAUnit.vhdl
Makefile		Makefile
OFUnit.o		OFUnit.o
OFUnit.vhdl		OFUnit.vhdl
README.md		README.md
SimpleRISC.o		SimpleRISC.o
SimpleRISC.vhdl		SimpleRISC.vhdl
armprocessor		armprocessor
conf		conf
documentation.pdf		documentation.pdf
e~simplerisc.o		e~simplerisc.o
fileRead.o		fileRead.o
fileRead.vhdl		fileRead.vhdl
input		input
run.sh		run.sh
simplerisc		simplerisc
work-obj93.cf		work-obj93.cf

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