The goal of this project is to improve the LEON3 core performance. To evaluate the new core we relied on a set of benchmarks: Dhrystone, Stanford, Whetstone, GMPbench, and MiBench suites, and a VIRTEX4 ML410 FPGA board. As a start point for this project we used the grlib-gpl-1.1.0-b4104.zip archive (provided by the course instructors but also available online). To improve the performance we rewrote the Multiplier and Divider implementations.

For more information please see the docs directory. It includes the assignment description, a report and a presentation.

This project was done for TU Delft course: Processor Design Project (ET4171). The contributors are Henrique Dantas and Luca Feltrin.