Tags: aws/aws-fpga
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Fix typo in date of Vivado version deprecation notice (#750) * Add EoL notice for F1 designs built with Vivado versions older than 2024.1 * Update table & deprecation notices * Fix typo in date --------- Co-authored-by: David Liu <gliuamz@amazon.com>
Add EoL notice for F1 designs built with Vivado versions older than 2… …024.1 (small shell branch) (#749) * Add EoL notice for F1 designs built with Vivado versions older than 2024.1 * Update deprecation dates * Fix date typo --------- Co-authored-by: David Liu <gliuamz@amazon.com>
rc 2.1.2 (#733) * Introduced Python Bindings to the SDK * Added [documentation](./sdk/userspace/cython_bindings/README.md) for Python binding usage and setup * [Examples](./sdk/userspace/cython_bindings/) demonstrating Python-based FPGA control * Added link to instructions for DCV licensing setup. Credit to @morgnza for this update! * Added verbiage to DCV setup guide to show where to set virtual display resolution * Fix to Bandwidth Calculation
rc v2.1.1 (#730) * Added global register offset for the SDE IP. * Added CL_SDE software exmaple for a user allocated DMA buffer. * Documentation to assist F2 customers with releasing AFIs and AMIs on the AWS Marketplace. * Documentation to assist in creating a virtual desktop based on the FPGA Developer AMI running graphics-intensive applications remotely on Amazon EC2 instances. * Fixed the BW calculation and tolerance calculation in the test_hbm_perf_random in the cl_mem_perf.
Releasing version 2.0.6 (#702) * Releasing CL_SDE software example to demonstrate how to use the Streaming Data Engine (SDE) DMA on small shell. * Fixing the virtual ethernet PacketGen Dual Instance Loopback example to forward packets back to the PacketGen instance. * Fixing DDR backdoor access in simulation.
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