Name		Name	Last commit message	Last commit date
Latest commit History 18 Commits
lab reports		lab reports
project_1		project_1
project_1_2		project_1_2
project_2_1		project_2_1
project_2_2		project_2_2
project_3_FSM		project_3_FSM
project_3_addition		project_3_addition
project_4_FIFO		project_4_FIFO
.gitattributes		.gitattributes
README.md		README.md

Repository files navigation

DigitalCircuits

UCAS-DigitalCircuits projects

a 4-bit adder
a 16-bit comparator
FSM
FIFO

Environment

Windows 11
Vivado 2017.4

About

UCAS-DigitalCircuits projects

Report repository

Releases

No releases published

Packages

Contributors

Languages

Verilog 100.0%