Design of a General Purpose Microprocessor

Features

• 180nm technique full custom design. 
  
• General purpose Multi-Cycle Microprocessor. 
  
• Consist of SRAM, ALU and Register Files. 
  
• Support 13 different instructions including: 
       memory instructions like LOAD STORE, 
       logic instructions like AND OR XOR, ADD instructions with 3 different burst lengths
      16-bit division instruction.  
  
• Optimized in terms of area, delay and power consumption.  
  
• Perl script used as decode stage of the processor(decoding instructions by generating input control signals)
  
• Result verification by perl script.
  
• Frequency:667MHz
  

Design Detail

Phase 1: Divider Design

See here

Phase 2: Microprocessor Overview

Our Microprocessor consists of three parts: SRAM, Register Files and ALU. Since we merged the divider with all other function units, multiply select signals and transmisstion gate have been designed to ensure the paths are correct to realize the operation of each intruction.

2.1 SRAM

This part we directly used the SRAM design in Lab2(part1 and part2). However we replaced the DFFs with Register Files here. What's more, I sized up the decoder and some other parts including the Read Circuit, and finally upgrade the accessor time to 1.2ns.

2.2 Register Files

Put 16 DFFs in a row, place them behind the SRAM. (TBC...)

2.3 ALU

We designed two ALUs, they are almost identical in terms of structure. Placing two ALUs here is a compromise after a trade-off between area and speed. With two ALU, each 16 bits, we could do 32 bits calcultions directly. The only difference between the two is the sizing of some paths due to their different positions in this processor.

Apart from the Divider designed in phase1, our ALU include a 16-bit Carry Bypass Adder, but it's upgraded to carry on all arithmatic and logic operations required.

2.4 Overall schematic

2.5 Perl Scripting

The perl code is CPU_vec_gen.pl. It reads the instruction file “cmd.txt”, and generate the corresponding vector file “CPU.vec” for the whole simulation process.