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pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog 1,435 328 Built by @andreaskurth @thommythomaso @micprog @suehtamacv @zarubaf 1 star today
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openhwgroup / cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

SystemVerilog 548 145 Built by @michael-platzer @zarubaf @lucabertaccini @davideschiavone @stmach 1 star today
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fpgasystems / Coyote

Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

SystemVerilog 316 91 Built by @bo3z @JonasDann @d-kor @maximilianheer @LuhaoLiu 0 stars today