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base repository: CompArchFA17/Lab2
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head repository: judycomparch/Lab2
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compare: master
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  • 5 commits
  • 6 files changed
  • 3 contributors

Commits on Oct 23, 2017

  1. Create workplan.txt

    xiaozhengxu authored Oct 23, 2017
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Commits on Oct 25, 2017

  1. inputconditioner logic seems to work, but the test bench is not compl… 

    …ete and doesn't stop by itself.
    Xiaozheng Xu committed Oct 25, 2017
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  2. Stopped infinite clock with finish. Test bench is almost complete. Ca… 

    …n test more debouncing
    Xiaozheng Xu committed Oct 25, 2017
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  3. Adding seemingly working shift register and midpoint

    Xiaozheng Xu authored and Xiaozheng Xu committed Oct 25, 2017
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Commits on Oct 26, 2017

  1. working midpoint on FPGA, modified input conditioner

    Xiaozheng Xu authored and Xiaozheng Xu committed Oct 26, 2017
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