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Commits on Oct 22, 2025

• Verilog: fix semantics of cover disable iff

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• Merge pull request #1352 from diffblue/unary_minus1-ext

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• Merge pull request #1340 from diffblue/verilog-size-cast

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• Verilog: extend test for unary minus and Boolean negation

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• Verilog: explicit casts are assignments

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• Merge pull request #1342 from diffblue/ports9-fix

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• Merge pull request #1350 from diffblue/four-valued-size-casts

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• Merge pull request #1349 from diffblue/power3-works

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• Merge pull request #1351 from diffblue/assignment-pattern-lhs1

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• Verilog: four-valued size casts

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• KNOWNBUG test for assignment pattern on LHS

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Commits on Oct 21, 2025

• Verilog: make power3 test work

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• Verilog: fix for port direction of output register ports

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• Merge pull request #1343 from diffblue/cover_sequence_statement

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Commits on Oct 20, 2025

• SVA: add cover sequence

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• Merge pull request #1347 from diffblue/dependabot/github_actions/actions/setup-node-6

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• Bump actions/setup-node from 5 to 6

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• Merge pull request #1339 from diffblue/size_cast-tests

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• Merge pull request #1341 from diffblue/ports9

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• Merge pull request #1344 from diffblue/cover_sequence5

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Commits on Oct 19, 2025

• SystemVerilog: KNOWNBUG test for cover disable iff

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• KNOWNBUG test for module port constraints

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• Verilog: Tests for explicit casts

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• Merge pull request #668 from diffblue/default_aval_bval_encoding

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• Merge pull request #930 from diffblue/reduction3

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• Merge pull request #1334 from diffblue/integer_literals2

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• Merge pull request #1335 from diffblue/integer_literals3

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• Merge pull request #1336 from diffblue/signing_cast1-ext

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• Verilog: test for signing casts

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Commits on Oct 18, 2025

• KNOWNBUG for unsized integer literals

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• Verilog: tests for unsigned integer literals

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• Verilog: default aval/bval lowering

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• aval/bval lowering for reduction operators

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• Merge pull request #1331 from diffblue/smv-enum-parse-tree

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• SMV: add enums to the parse tree

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